1. Field of the Invention
The present invention is related to an improvement of a timing phase synchronization detecting circuit and a demodulator in a wireless (radio) communication field.
2. Description of the Related Art
FIG. 13 is a structural diagram for representing a conventional timing phase synchronization detecting circuit described in, for instance, U.S. Pat. No. 4,675,558.
In FIG. 13, reference numeral 101 shows a rectangular input signal having either a value of "A" (symbol "A" being a positive value) or a value of "-A"; reference numeral 102 indicates a clock; reference numeral 103 represents a timing phase synchronization signal for indicating as to whether or not a timing phase synchronization can be established between a Nyquist point of the input signal 101 and the clock 102; and reference numeral 111 shows a low-pass filter. Also, reference numeral 104 indicates a signal obtained by filtering the input signal 101 by the low-pass filter 111; reference numeral 131 denotes a NAND gate; and reference numeral 105 indicates a logic value outputted from the NAND gate 131. Then, reference numerals 112 and 113 are low-pass filters; reference numerals 121, 122, 123 show comparators; reference numeral 132 is a NOT gate; reference numerals 133 and 134 represent flip-flops; reference numeral 135 indicates a differentiator; and reference numeral 106 is an output result of the differentiator 135.
In this conventional timing phase synchronization detecting circuit, the comparator 121 first compares A/2 with the amplitude value of the signal 104. If the amplitude value of the signal 104 is smaller than, or equal to A/2, then the comparator 121 outputs either a logic "1" or "HIGH". Conversely, if the amplitude value of the signal 104 is larger than A/2, then the comparator 121 outputs either a logic "0" or "LOW".
Similarly, if the amplitude value of the signal 104 is larger than, or equal to -A/2, then the comparator 122 outputs either a logic "1" or "HIGH". Conversely, if the amplitude value of the signal 104 is smaller than -A/2, then the comparator 122 outputs either a logic "0" or "LOW".
The signal 105 corresponds to an output result of the NAND gate 131 in such a case that the output results of the comparators 121 and 122 are inputted to the NAND gate 131. In other words, when the value of the signal 104 is smaller than, or equal to -A/2, otherwise larger than A/2, then signal 105 represents either logic "1" or "HIGH", whereas when the value of the signal 104 is larger than -A/2, and also smaller than, or equal to A/2, the signal 105 indicates either a logic "0" or "LOW".
Next, in the flip-flops 133 and 134, the signal 105 is sampled in response to the respective rising edges and falling edges of the clock 102. The LPF 112 averages the value produced by sampling the signal 105 in response to the rising edge of the clock 102, and the LPF 113 averages the value produced by sampling the signal 105 in response to the falling edge of the clock 102 by employing the method of moving averages.
Next, in the differentiator 135, the output filtered from the LPF 113 is subtracted from the output filtered from the LPF 112 to output a differentiated value.
Finally, the comparator 123 compares the differentiated value 106 obtained from the differentiator 135 with a threshold value V.sub.REF. In the case that the differentiated value 106 of the differentiator 135 is larger than, or equal to V.sub.REF, the comparator 123 outputs either "1" or "HIGH" indicative of a timing phase synchronous condition as a timing phase synchronization signal 103. In the case that the differentiated value 106 of the differentiator 135 is smaller than V.sub.REF, the comparator 123 outputs either "0" or "LOW" indicative of a timing phase asynchronous condition as the timing phase synchronization signal 103.
FIGS. 14A and 14B show an example of timing charts for the respective signals in the conventional timing phase synchronization detecting circuit. As seen from FIG. 14A, under such a condition that the rising edge of the clock 102 impinges at a point near the Nyquist point of the signal 104, the signal 105 sampled in response to the rising edge of the clock 102 indicates the value of "HIGH", whereas the-signal 105 sampled in response to the falling edge of the clock 102 indicates either "HIGH" or "LOW".
Conversely, under such a condition that a timing phase difference between the rising edge of the clock 102 and the Nyquist point of the signal 104 is large (see FIG. 14B), if there is a change in the data, then the signal 105 indicates the value of "LOW", whereas if there is no change in the data, then the signal 105 indicates the value of "HIGH".
Also, under such a condition that a timing phase difference between the rising edge of the clock 102 and the Nyquist point of the signal 104 is large, if the signal 105 is sampled in response to the falling edge of the clock 102, then the signal 105 indicates the value of "HIGH".
As a result, in such a case that the rising edge of the clock 102 impinges at the point near the Nyquist point of the signal 104, since the output signal of the LPF 112 becomes larger than the output signal of the LPF 113, the logic value of the timing phase synchronization signal becomes the value of either "1" or "HIGH" indicative of the timing phase synchronous condition (FIG. 15).
Conversely, in the case that the timing phase difference between the rising edge of the clock 102 and the Nyquist point of the signal 104 is large, since the output signal of the LPF 112 becomes smaller than that of the LPF 113, the logic value of the timing phase synchronization signal 103 becomes the value of either "0" or "LOW" indicative of the timing phase asynchronous condition (FIG. 15). As previously described, in the conventional timing phase synchronization detecting circuit, it is possible to judge as to whether or not the input signal 101 is synchronized with the clock 102 based upon the logic value of the timing phase synchronization signal 103.
As previously explained, in the conventional timing phase synchronization detecting circuit, since the establishment of the timing phase synchronization is judged by employing the amplitude information of the input signal, the AGC (Automatic Gain Control) circuit is required in such a case that the variation in the amplitude value of the input signal is large. Also, the complex and large-scaled circuit arrangement of the demodulator is required. There is another problem that since the random pattern is employed as the reception signal, the detection precision of the timing phase synchronization would be deteriorated, depending upon differences in the received data stream.
Then, there is another problem in the conventional frequency synchronizing means for performing the carrier frequency synchronization with employment of the baseband signal sampled at the symbol rate (refer to, for instance, "ARRANGEMENT AND CHARACTERISTICS OF 384 kbps--.pi./4 SHIFT QPSK BURST DEMODULATOR" written by YAMAMOTO et al., Japanese Telecommunication Institute Technical Report RCS 92-100), and also in the conventional carrier recovering means for performing the carrier recovery (refer to, for example, "ADAPTIVE CARRIER SYNCHRONIZATION (ACT) DEMODULATION SYSTEM FOR QPSK MOBILE WIRELESS TRANSMISSION" written by SAITO et al., Japanese Telecommunication Institute Report Vol. J75-B-II No. 8, pages 499 to 507, issued in August 1992). That is, in such a case that the timing phase synchronization cannot be established between the recovered clock outputted from the timing recovering means and the Nyquist point of the baseband signal, the frequency synchronization characteristic and the jitter characteristic of the recovered carrier phase, which have been obtained by executing the frequency synchronizing means, are largely deteriorated, as compared with those obtained when the timing phase synchronization is established. As a consequence, the timing synchronization detecting operation cannot be applied until the recovered clock has completely captured the Nyquist point of the baseband phase signal.
Moreover, there are other problems. When the frequency range of the PLL is widened in the conventional timing recovering means, the highspeed timing recovering operation can be carried out. However, the jitter component of the recovered clock after the capture operation becomes large. Conversely, when the frequency range of the PLL is made narrow, although the jitter component of the recovered clock after the capture operation can be reduced, the timing phase capture operation would be delayed.